I2c Overview May 2026

Each slave device has a unique 7-bit (or 10-bit) address, eliminating the need for complex Chip Select (CS) lines used in SPI.

I2C communication is master-controlled. The master initiates, manages, and terminates communication, generating the clock signal.

The master sends the 7-bit unique address of the target slave, followed by a R/W bit (0 for write, 1 for read).

Multiple masters can control the same slave, and multiple slaves can reside on the same bus.

Data is sent in 8-bit bytes, most significant bit first, with each byte followed by an ACK/NACK bit.

The master releases the SDA line to high while SCL is high, signaling the end of transmission. Advantages and Limitations Understanding I2C